1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a method of fabricating DRAM device.
2. Background of the Invention
In a DRAM device, in which an NMOS device with a low threshold voltage is adopted with a triple-well structure, two different kinds of transistors are additionally required, as compared with a device with a twin-well structure, as shown in a table below.
TABLE ______________________________________ NMOS LVTN NMOS LVTN PMOS Cell TR (VBB = (VBB = (VBB = (VBB = (VBB = (VBB = 0V) 0V) 1V) 1V) 0V) 1V) ______________________________________ Twin-well X X .smallcircle. .smallcircle. .smallcircle. .smallcircle. Triple-well .smallcircle. .smallcircle. .smallcircle. .smallcircle. .smallcircle. .smallcircle. ______________________________________
As can be seen from the above table, in a twin-well structure, the P well is not isolated from the semiconductor substrate by a deep N well. Therefore, a well bias voltage is the same as that of the cell transistor. In a triple-well structure as shown in FIG. 1, a peripheral well (the semiconductor substrate 100) and a pocket well 140 are isolated from each other. Consequently, the well bias can be set differently. In the triple well structure, the pocket well includes a cell transistor improving the refresh characteristics, while the peripheral well improves the short channel effect. By adding the pocket P-well and the peripheral well to the triple-well structure, the threshold voltage for every transistor has to be separately adjusted. As a result, an additional photolithographic process for ion implantation is required. Such an additional process, however, increases the DRAM manufacturing cost.